1. Field of the Invention
The present invention relates to a high-speed, high-precision comparator circuit that can compare two weak signals and output a digital comparison result value in, for example, a high-speed analog-to-digital converter.
2. Description of the Related Art
Known comparators used in analog-to-digital converters include a differential amplifier circuit and a latch circuit that outputs a digital value synchronized to a clock signal. One example is shown in FIG. 1. The differential amplifier circuit has n-channel metal-oxide-semiconductor (NMOS) transistors M1, M2 coupled to a current mirror load circuit comprising p-channel metal-oxide-semiconductor (PMOS) transistors M3, M4, M5, M6. The latch circuit comprises NMOS transistors M7, M8, M9 and PMOS transistors M10, M11, M12.
In the differential amplifier circuit, the sources of transistors M1, M2 are connected to a current source I1, their gates receive input signals INP, INN, and their drains are connected to the drains and gates of transistors M3, M4 and the gates of transistors M5, M6. The sources of transistors M3, M4, M5, M6 receive a power supply voltage VDD; the drains of transistors M5, M6 are connected to the output terminals OUTP, OUTN of the comparator.
In the latch circuit, transistors M7, M11 constitute an inverting amplifier, which is cross-coupled to another inverting amplifier comprising transistors M8, M12, and is coupled to the input and output terminals OUTP, OUTN. Transistors M9 and M10 synchronize the operation of the inverting amplifiers with a clock signal (CLK) which they receive at their gates. Transistor M9 is inserted between the output terminals OUTP, OUTN; transistor M10 is inserted between the sources of transistors M11, M12 and the power supply. The sources of transistors M7, M8 are connected to ground.
This conventional comparator circuit operates as follows.
When the clock signal CLK is high, transistor M9 conducts, equalizing the output terminals OUTP, OUTN to the same potential, while transistor M10 is taken out of conduction, inactivating the latch circuit. Any potential difference between the input signals INP and INN is amplified by transistors Ml-M4, but as the output terminals OUTP, OUTN are equalized, amplification is confined to the differential amplifier circuit.
Next, when the clock signal CLK goes low, transistor M9 is taken out of conduction and transistor M10 conducts, activating the inverting amplifiers in the latch circuit. Current mirror transistors M5, M6 transfer the amplified potential difference from the differential amplifier circuit to the output terminals OUTP and OUTN. The cross-coupled inverting amplifiers formed by transistors M7, M8, M11, M12 amplify the potential difference further so that the potentials at the output terminals OUTP, OUTN diverge to the power supply level and the ground level. The latch circuit then holds the output terminals OUTP, OUTN at these levels.
One example of this type of comparator is disclosed in Japanese Patent Application Publication No. 5-67950.
A problem that occurs in this type of comparator is that the output levels are affected by switching noise. More specifically, the high-to-low transition of the clock signal that activates the latch circuit is capacitively coupled through transistor M9 to the input and output terminals OUTP, OUTN. As shown in FIG. 2, accordingly, at the fall of the clock signal (CLK), the output potentials (OUTP, OUTN) dip temporarily toward the ground level before they begin to diverge. The divergence of the output potentials to the power-supply and ground levels (equal to the high and low logic levels of the clock signal) is accordingly delayed, slowing the response of the comparator circuit.